High-speed data communication integrated circuit (IC) dies include both drivers and receivers. The driver of one such IC connects to the receiver of another IC via a signal transmission line. The signal transmission line includes, in an example embodiment, a trace of a printed circuit (PC) board that electrically couples the driver to the receiver. Such driver and receiver circuits may be used, for example, in Double Data Rate (DDR) interfaces, which may include a POD (pseudo open drain) termination scheme. DDR interfaces are configured to transmit and receive data on both rising and falling edges of a timing signal.
The description above is presented as a general overview of related art in this field and should not be construed as an admission that any of the information it contains constitutes prior art against the present patent application.